![]() ![]() ījörk M, Hayden O, Schmid H, Riel H, Riess W (2007) Vertical surround-gated silicon nanowire impact ionization field-effect transistors. In: 2018 IEEE international reliability physics symposium (IRPS), pp 6F.4–1–6F.4–6. Rahman A, Dacuna J, Nayak P, Leatherman G, Ramey S (2018) Reliability studies of a 10nm high-performance and low-power cmos technology featuring 3rd generation finfet and 5th generation hk/mg. ĭel Alamo JA (2011) Nanometre-scale electronics with iii–v compound semiconductors. Įhteshamuddin M, Loan SA, Rafat M (2018) Planar junctionless silicon-on-insulator transistor with buried metal layer. Loan SA, Qureshi S, Iyer SSK (2010) A novel partial-ground-plane-based mosfet on selective buried oxide: 2-d simulation study. Horowitz M, Alon E, Patil D, Naffziger S, Kumar R, Bernstein K (2005) Scaling, power, and the future of cmos, in IEDM Tech. Henson WK, Yang N, Kubicek S, Vogel EM, Wortman JJ, De Meyer K, Naem A (2000) Analysis of leakage currents and impact on off-state power consumption for cmos technology in the 100-nm regime. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction ( \(\sim \)4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device. The switching characteristics is shown to have an overshoot of \(\sim \)0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In addition, butterfly curves show symmetric high (NM H) and low (NM L) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. Simulations carried out using calibrated parameters show better drive current (≈ 10 − 2 − 10 − 3A/ μ m) compared to the quantum tunneling current in simulated state-of-the-art multifunctional devices (≈ 10 − 4 − 10 − 5A/ μ m). In practice, metal-silicides such as erbium/ytterbium silicide (ErSi x/YbSi x) for the n-drain and platinum silicide (PtSi) for the p-drain can be used as they provide smallest electron and hole Schottky-barrier heights (SBHs). ![]() It employs n +/ p +- i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. The device uses a dual fin structure having a single mid-gap workfunction gate ( \(\sim \)4.65 eV) alongside dual metal (metal-silicide) drain regions. ![]() The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. ![]()
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